Replacing conventional silicon oxide (e.g. SiO2) gate dielectrics with silicon oxynitride (SiON) layers for MOS transistors is known to reduce gate dielectric leakage and boron (B) penetration from the gate electrode (for P+ polysilicon gate for PMOS) into the underlying semiconductor surface which can result in threshold voltage (Vt) shifts. A conventional method to form a SiON gate dielectric layer includes thermal oxidation of a silicon comprising surface to form a silicon oxide “base” dielectric, followed by a plasma nitridation to incorporate nitrogen (N) throughout the silicon oxide dielectric, and then a thermal post nitridation anneal in O2/N2 at a temperature around 1,100° C.
The higher the N concentration in the SiON dielectric, the higher its dielectric constant which allows the use of a thicker dielectric film for a given equivalent oxide thickness (EOT). The thickness of the SiON layer may be expressed as an EOT which is a parameter used to compare the performance of MOS transistors having a high-k dielectric layer with the performance of MOS transistors having a silicon dioxide gate dielectric layer. The EOT is defined as the thickness of a silicon dioxide gate dielectric needed to obtain the same gate capacitance as that obtained with a gate dielectric having a higher dielectric constant k as compared to silicon dioxide (the k of SiO2 is about 3.9). For example, an EOT of 1 nm would result from the use a 10 nm thick high-k dielectric that has a k value of 39.
With ever increasing N concentrations within the gate dielectric, the process has become susceptible to reduced Gate Oxide Integrity (GOI) and/or increased Early Failure Rates (EFR), notable along gate dielectric edges. Within the wafer fab engineering community, this is referred to as elevated polysilicon finger failures when similarly sized (area) polysilicon block structures fail at a reduced rate compared to polysilicon fingers which are structures with a higher ratio of polysilicon edge area per total unit area. Most work to address this problem has been directed at improving the silicon oxide base dielectric quality, or reducing the gate etch depletion effect (e.g., by changing the etch conditions).